Surface imaging lithography is a major requirement for patterning current integrated circuit layers. Small critical dimensions coupled with severe wafer topography and radiation reflection from the integrated circuit surface make the patterning of certain integrated circuit levels extremely difficult using standard lithographic techniques. Further, the use of high numerical aperture or short wavelength steppers reduces the focus budget for any lithography process. Consequently, the patterning of most levels for advanced circuit technologies requires the use of new non-standard lithographic processes.
Three basic surface-imaging technologies have been heretofore proposed. A first of these basic technologies is the group of single-layer technologies, including the DESIRE.RTM. process. Other surface-imaging technologies include bilayer processes, including SABRE, and various trilayer processes.
The DESIRE.RTM. process was introduced by B. Roland, R. Lombaerts and F. Coopmans in their paper "DESIRE: A New Approach for Silicon Incorporation In Dry Developed Resists", 1986 Dry Process Symposium, Pages 98-103. This process requires the use of a special resist. Only negative-tone resist for the DESIRE process is currently available, which leads to duplication of stepper reticles as well as to limitations for exposing levels such as contacts. This process is sensitive to many process parameters and requires tight control of silylation and etching conditions, especially temperatures, to obtain reproducible results.
With standard bilayer processes, a special resist is required for the top layer, which doubles as both the imaging and the silylable layer. No resist combining these two functions in an acceptable manner has been commercially available. One of the major drawbacks of the standard bilayer processes is the swelling of the imaging layer during silylation. Typical of the standard bilayer processes is the process disclosed in McColgin, William C et al. "Silicon-Added Bilayer Resist (SABRE) System", Proceeddings SPIE, Volume 920 pages 2-9.
Finally, there are trilayer processes. In these processes, the following problems are associated with the use of an oxide, or any other masking material, to form the intermediate layer: cracking of the resist due to different thermal expansion coefficients for the intermediate and bottom/top layers, particle formation during the deposition of the intermediate layer, and difficult cleaning of the hard-baked bottom layer. To summarize, several schemes have been proposed to solve problems associated with high-relief integrated circuit topography and radiation reflection problems. Nevertheless, a need persists in the industry for a microlithography system that demonstrates the processing and manufacturing characteristics necessary for acceptance as a standard lithography technique.